Identification interrogation system



Sept. 28, 1965 R. K. DAVIS ETAL 3,209,350

IDENTIFICATION INTERROGATION SYSTEM Filed Oct. 4, 1965 12 Sheets-Sheet lA I9 I 58 AMP '2 I I3 ll I3 480-370 770-660 630-520 SWEEP GIC CLOCKCLOCK CLOCK 4 48O'37O 770-660 630'520 J C O NTR 0 l I I I IN VEN TOR.

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IDENTIFICATION INTERROGATION SYSTEM Filed Oct. 4, 1963 12 Sheets-Sheet12 FIG.6

AMPLIFIER LOGIC AMPLIFIER AND NOT M) (F) (E) AND NOT FIG.6A FIG.6C

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United States Patent 3,209,350 IDENTIFICATION INTERROGATION SYSTEMRichard K. Davis and Ronald E. Gareis, Roanoke, Va., assignors toGeneral Electric Company, a corporation of New York Filed Oct. 4, 1963,Ser. No. 313,877 6 Claims. (Cl. 343-6.5)

This invention relates to a system for identifying objects passing, orbeing passed by, an interrogation device. More specifically thisinvention relates to a system for identifying objects, each objecthaving a unique identifica tion device with a provision for assuringthat the proper identification is obtained from the identificationdevice.

This invention is particularly directed to that type of identificationsystem where the unique identification device associated with eachobject uses piezoelectric elements, each having a different preselectedfrequency response, whereby identification of the object is made by thepiezoelectric elements connected in the unique identification device.

In such an identification system, the piezoelectric elements in eachidentification device have different preselected frequency responses.Signals are transmitted over a preselected frequency range from atransmitting antenna. Signals at the same frequencies of thepiezoelectric elements connected in the identification device arerepeated by the identification device, transmitted to a receivingantenna and decoded to indicate the identity of the object as indicatedby the identification device.

It is particularly important that the signal strength is at a maximumwhen the identification information is read.

It is therefore an object of this invention to provide a new andimproved identification interrogation system.

Another object of this invention is to provide a new and improvedidentification interrogation system which will insure that all of theidentification information is read from the identification device.

Yet another object of this invention is to provide a new and improvedidentification interrogation system using piezoelectric elements whichwill insure that the signals from all of the piezoelectric elements willbe received.

It is another object of this invention to provide a new and improvedidentification interrogation system having transmitting and receivingantennas which will insure that the identification information will beread when the entire identification device is within the field of theantennas.

Very briefly then, this invention consists of a system having a signaltransmitting device and a transmitting antenna preferably operating atradio frequencies, a corresponding receiving device and receivingantenna suitably arranged to cooperate with the transmitting device, aselective signal repeating device carried by the object to beidentified, and logic circuits for correlating the identification of theobject with the transmitted signal. A second receiving antenna withassociated logic is provided to insure that the selective signalrepeating device is within the field of the transmitting and receivingantenna before the logic circuit correlates the identification of theobject with the transmitted signal.

This invention is set forth with particularity in the appended claims.The principles and characteristics of the invention, as well as otherobjects and advantages are 3,209,350 Patented Sept. '28, 1965 revealedand discussed through the medium of the illustrative embodimentsappearing in the specification and drawings which follow.

In the drawings:

FIG. 1 shows how to put FIGS. la-c together.

FIGS. 1ac is a block diagram of an identification system constructed inaccordance with the principles of this invention.

FIG. 2 shows the timing diagram of the signals controlling the operationof the identification system.

FIG. 3 shows the frequencies used in the identification system.

FIG. 4 shows how to put FIGS. 4a through 4 together.v

FIGS. 4a through 4 when put together as shown in FIG. 4, is a circuitdiagram of an embodiment of this invention.

FIG. 5 is a circuit diagram of the shift register and associatedcircuits shown in block form in FIG. 1.

FIG; 6 shows the symbols for the circuits as blocks in FIGS. 4a through4 and FIG. 5.

Referring now to FIG. 1, sweep oscillator 11 sweeps over the frequenciesfrom 520 kc. to 630 kc. Sweep oscillator 12 sweeps over the frequenciesfrom 660 kc. to 770 kc. Sweep oscillator 13 sweeps over the frequenciesfrom 370 kc. to 480 kc. Amplifier 14 amplifies the signals produced bysweep oscillators 11-13. Transmitting antenna 15 is a closed loopantenna for transmitting the signals produced by sweep oscillators 11-13and amplified by amplifier 14. A receiving antenna 16 is isolated fromtransmitting antenna 15 by overlapping the antennas in the same plane sothat normally the receiving antenna 16 does not receive the signaltransmitted from transmitting antenna 15. A length of 30 to 50 inches isa good length for the antennas. Receiving antenna 17 is also isolatedfrom transmitting antenna 15 by overlapping the antennas in the sameplane so that normally receiving antenna 17 does not receive the signalstransmitted from transmitting antenna 15. Receiving antenna 17 is of asmaller length than transmitting and receiving antennas 15 and 16 and isnormally of a length of approximately 15 to 25 inches.

Receiver 18 receives over the frequencies from 370 through 770 kc. Gatereceiver 19 receives over the frequencies from 450 to 480 kc. The digitrepresented by Group A of FIG. 3 must never be zero for the system tooperate.

Signal repeating device 20 has twelve piezoelectric elements 21 through32 connected in parallel through capacitor 33 to a pickup antenna 34.The piezoelectric elements 21-32 are selected from 36 differentfrequencies 370 kc. through 770 kc. as indicated vin the timing chart inFIG. 3. y

The piezoelectric elements may be small discs of lead,zirconate-titanate, or barium titanate. They may also be constructed ofother materials which have a piezoelectric effect. Piezoelectricelements of lead zirconatetitanate have a resonant frequency tolerancewithin 0.1% from 40 C. to C. The resonant frequency is estimated tochange no more than :0.2% in 10 years.

The piezoelectric elements of lead zirconate-titanate have a minimumimpedance of approximately 15 ohms at resonance. At a nonresonancefrequency, their impedance is of the order of 1000 ohms.

Each signal repeating device 20 therefore has a low impedance at thefrequencies of the piezoelectric devices connected into the pickupantenna 34 and a high impedance at the other frequencies.

Each signal repeating device 20 is coded in binary form to represent anidentification number identifying the object to which the signalrepeating device 20 is connected.

Referring now to FIG. 3. The 36 piezoelectric elements are divided into9 different groups of four piezoelectric elements each. Each group of 4piezoelectric elements may be coded in a l, 2, 4, 7 code to representone decimal number. The combination of these indicates the identity ofthe object to be identified.

The coding of a 1, 2, 4, 7 code to represent a decimal number is asfollows. An X is indicatedwhen that bit is to be a binary one, and awhen that bit is to be a binary zero to represent the indicated decimalnumber.

Each group of four piezoelectric elements may be coded into a decimalnumber as indicated above to make a nine digit number. Although thereare 36 binary bits and 36 different frequencies involved, only twelvepiezoelectric elements are connected to each signal repeating device 20.This is because the absence of a piezoelectric element indicates abinary zero. An examination of the 1, 2, 4, 7 coding table will quicklyshow that in coding the decimal numbers zero through nine, out of fortyrequired bits, twentysix are binary zeros, while only fourteen arebinary ones. Considering that in putting together a nine digit number,there will be decimal zeros in many of the numbers, it is evident thatan average twelve piezoelectric elements in each signal repeating devicewill sufiice. A maximum of eighteen elements may be required for somenumbers.

The receiver antenna 16 in FIG. 1 overlaps the transmitter antenna 15somewhat, causing electromagnetic fiux from the transmitter antenna 15to link the receiver antenna 16 partly in one direction through the loopand partly in the other direction through the loop. The effect onreceiver coil 16 is that at any instant the net flux linking thereceiver coil 17 and the transmitter coil 15 is zero and no signal isproduced in receiver coil 15.

Each clock 41-43 contains twelve piezoelectric elements, asindicatedinthe following table:

Piezoelectric Element Frequencies Clock 41 Clock 42 Clock 43 Each clock41-43 is driven by a corresponding sweep oscillator 11-13 so that eachclock 41-43 produces a signal at a predetermined time in synchronismwith the production of a corresponding frequency by the correspondingsweep oscillator. Each clock contains a piezoelectric element at thefrequencies shown in the above table.

The distance from the transmitter-receiver antennas to the pickupantenna 34 is largely a matter of the size of the receiving andtransmitting antennas and the pickup antennas. A range of four to sixinches is a good separating distance. A good rule of thumb is that thedistance from the transmitter-receiver antennas to the pickup antennasis a maximum of times the width of a square pickup antenna or times thediameter of a round antenna. The pickup antenna should pass in a planeparallel to the plane of the transmitter-receiver antenna for maximumsignal, but can pass at an angle to the antennas with a correspondingdecrease in received signal.

The gate receiver 19 is connected to a reset sweep circuit 45.

Reset sweep 45 is connected to sweep oscillators 11- 13, and to logic47. Logic element 47 is connected to readout control circuit 49, gate51, shift registers 52-54, transfer circuits 55-57 and buffer registers58-60.

Readout control circuit 49 is connected to transfer circuits 61-69. Thereadout control circuit 49 is also connected to the punch 71. Transfercircuits 61-69 are connected to the decoder 73. Buffer register 58 isconnected to three transfer circuits 61-63, buffer register 59 to threetransfer circuits 64-66, and buffer register 60 to three transfercircuits 67-69.

The reset sweep 45 automatically resets each of the sweep oscillators11-13 after they have swept through the first four frequencies eachtime. When a signal is received by reset sweep 45 from the gate receiver19, the reset sweep is de-activated and does not reset the sweeposcillators 11-13.

The identity signals are received and transmitted from the receiver 18through the logic element 47. Logic element 47 does not pass on theidentity signals until a signal is received from gate receiver 19. Uponreceiving a signal from the gate receiver, the logic element 47 passesthe identity signals to shift registers 52-54.

After the identity signals have been read into the shift registers52-54, a signal from the logic element 47 applied to transfer elements55-57 will transfer the information therein to the buffer registers58-60. After all information has been shifted in the shift registers52-57, the readout control applies a signal to transfer elements 61-69in sequence for readout. The information stored in the shift registers52-57 is read out in serial form one decimal bit at a time throughdecoder 73 and punched out by punch 71.

Operation Signal repeating devices 20 are attached to the objects to beidentified so that the signal repeating devices will pass through theradiation fields of the antennas 15, 16 and 17 as the object moves in apredetermined path.

Each signal repeating device is coded to a different identificationnumber so that each signal repeating device is a unique identificationdevice. The identification number is selected by the twelvepiezoelectric elements connected in the signal repeating device 20 asdescribed hereinbefore. The twelve piezoelectric elements are selectedfrom the thirty-six different frequencies.

Sweep oscillators 11-13 generate signals starting at the upper end oftheir frequency range. Reset sweep 45 continually resets sweeposcillators 11-13 after they have swept through their first fourfrequencies. In this manner sweep oscillator 11 sweeps through the 480kc. to 450 kc. frequencies and then is reset to start its sweep again.

The variable frequency signals produced by sweep oscillators 11-13 areamplified by amplifier 14 and transmitted by transmitting antenna 15. Assoon as a signal repeating device 20 enters the field of the receivingantenna 16, one or more signals are received at the first fourfrequencies produced by sweep oscillators 11-13 depending on theparticular piezoelectric elements connected in that specific signalrepeating device 20. The signals received by receiving antenna 16 areapplied by receiver 18 to logic element 47. The logic element 47 isinhibited from passing the signals from receiver 18 this time.

Clocks 41-43 produce signals synchronized with the frequencies shownhereinbefore as produced by sweep oscillators 11-13. The clock signalsproduced by clocks 41-43 are inhibited by gate 51.

When an object moves so that the attached signal repeating device 20enters the field of receiving antenna 17, one or more signals arereceived at the first four frequencies produced by sweep oscillator 11,depending on the particular piezoelectric elements connected in thatparticular signal repeating device. The signals received by receivingantenna 17 are applied to the gate receiver 19. Gate receiver 19 appliesa gate signal to reset sweep 45 and logic element 47. The reset sweep 45resets the sweep oscillators 11-13 and is then turned off so oscillators11-13 can sweep. through their whole frequency range. Logic element 47is enabled so that signals applied to the logic element 47 from receiver18 will be passed by the logic element 47 and the logic element 47applies a signal to gate 51 to open the gate 51.

The turning off of the reset sweep 45 by the gate receiver 19 and theenabling of the logic element 47 by the gate receiver 19 indicates thata signal repeating device 20 is well within the field of the receivingantenna 16. The sweeping of the first four frequencies and thenresetting the sweep oscillators to begin a new sweep until a signalrepeating device is within the field of the receiving antenna 16 permitsthe use of a shorter antenna than would be required to sweep the wholefrequency range seeking the presence of a signal repeating device.

The variable frequency signals produced by sweep oscillators 11-13 areamplified by amplifier 14 and transmitted from transmitting antenna 15.At the frequencies of the piezoelectric elements connected to pickupantenna in signal repeating device 20, the transmitting antenna 15 andthe receiving antenna 16 are coupled to apply signals to receiver 18.Receiver 18 produces output pulses at the frequencies of thepiezoelectric elements connected in signal repeating device 20 andapplies these pulses to logic element 47. The logic element 47 passesthe signals from the receiver 19 to the inputs of shift registers 52-54.The signals from the clocks 41-43 shift the identification code in theshift register 52-54.

After the identification code has been stored in shift registers 52-54,a sginal from logic 47 is applied to transfer elements 55-57 to transferthe identification code from the shift registers 52-54 to bufierregisters 58-60. After the identification code has been transferred tothe bulfer registers 58-60, the readout control 49 responds to a signalfrom the logic element 47 to control the sequential readout of theidentification code by applying sequential signals to transfer elements61-69. The identification code is decoded in decoder 73 and punched outby a punch '71.

Symbols and nomenclature In the following detailed description, the termone signal when used refers to a -6 volt signal and the term zero signalrefers to a 0 volt signal or ground potential.

The symbols used in FIGS. 6a through 6l and described hereinafter areused in the detailed description of the identification system.

In all of the elements shown, input terminals are usually shown on theleft side of the symbols and output terminals are shown on the rightside of the symbols.

Amplifier FIG. 6a shows the symbol for the amplifier. A one signal onthe input terminal will cause current to flow in a load connectedbetween the output terminal and the negative power bus.

Logic amplifier FIG. 6b shows the symbol for the logic amplifier orinverter amplifier. The signal applied to the input terminal is invertedand produced on the output terminal after amplification.

AND/NOT circuit FIG. 60 shows the symbol for the AND/NOT circuit. Itsoperation is such that a zero signal on all input terminals causes a onesignal to be produced on the output terminal. This unit may have two ormore input terminals. Positive pulses received on all terminals areeffectively the same as zero signals received and cause a one signal tobe produced on the output terminal. If a one signal is applied to one ormore input terminals, a Zero signal is produced on the output terminal.

Counter FIG. 6d shows the symbol for a counter bit. A one signal appliedto the SET terminal sets the counter bit to one, so that a one signalappears at the 1 output terminal and a zero signal at the 0 terminal.This one signal at the 1 output terminal will be maintained after theset signal is removed and remains until a one signal is applied to theRST (reset) terminal, at which time the one signal at the 1 outputterminal becomes a zero signal; and .a one signal appears at the 0output terminal. The counter bit will remain in this, the zero state orreset state, until a one signal is again applied to the SET terrninal.In addition, a positive pulse received on the PUL input terminal willcomplement the counter bit, changing the state of the counter bit fromthe previous state. The shift of the counter bit will occur on thepositive going side of the input pulse. The l and 0 output terminals arealways the inverse of each other unless a one signal is simultaneouslyapplied to the SET and RST (reset) ter minal, in which case, a zerooutput signal will be present on both output terminals.

Inverter FIG. 6e shows the basic symbol for the inverter. A one signalis produced on the output terminal if a zero signal is received on theinput terminal and a zero signal is produced on the output terminal if aone signal is received on the input terminal. The small circle is addedto the output terminal to indicate the inverted output signal.

Inverting OR circuit FIG. 6f shows the symbol for the inverting ORcircuit. Its operation is such that one or more one signals applied tothe input terminals will cause a zero signal to be produced on itsoutput terminal. The small circle is added to the output terminal toindicate the inverted output signal.

On shot pulse generator FIG. 6g shows the symbol for one shot pulsegenerator. A negative going pulse or a negative going step change in aDO input to the upper input terminal, or a positive going pulse or apositive going step change in a DC. input to the lower input terminal,will cause a pulse to be produced at the upper output terminal with anegative going leading edge and a pulse to be produced at the loweroutput terminal with a positive going leading edge. Both output pulsesare available at the same time with a signal on either or both inputterminals. The length in time of the output pulses may be adjusted bythe capacitance of a capacitor connected to the one shot pulsegenerator.

0R circuit FIG. 6h shows a symbol for an OR circuit. Its operation issuch that a one signal on either input terminal will produce a onesignal on the output terminal. This symbol may have two or more inputterminals.

Sh i f register FIG. 6i shows a symbol for a shift register bit. Thiscircuit is similar to the counter bit shown in FIG. 6d

7 and described above, except for the provision of the ST1 (steer l) andthe STO (steer terminals. If a one signal is applied to the SETterminal, the shift register bit is set to one; and a one signal willappear at the 1 output terminal. This one signal will remain after theset signal is removed, with the shift register bit remaining set to oneuntil it is reset. A one signal applied to the RST (reset) terminal willreset the shift register bit to zero, and a one signal will appear atthe 0 output terminal. The shift register bit will remain reset until itis set to one again. If one signals are received simultaneously on boththe RST and the SET terminals, a zero output signal will be present onboth output terminals. In addition, if a one signal is applied to theST1 (steer 1) terminal, a zero signal to the STO terminal and a positivepulse applied to the PUL terminal, the shift register bit will be set toone with a one signal appearing on the 1 output terminal. If a onesignal is applied to the STO (steer 0) terminal, a zero signal to theST1 terminal and a pulse applied to the PUL terminal, the shift registerwill be reset to zero with a one signal apperaing on the 0 outputterminal. Th shift of signals from terminal to terminal occurs on thepositive going side of the positive pulse applied to the PUL inputterminal. The l and 0 output terminals are always the inverse of eachother, unless a one signal is simultaneously applied to the ST1 and theSTO terminals, in which case the output remains as it was before.

Flip-Flop FIGURE 6j shows the symbol for the flip-flop element. If asignal is applied to terminal F or H (the set terminals), the flip-flopwill be set to 1 with a signal appearing at terminal E. This signal willbe maintained after the set signal is removed with the flip-flopremaining set at l. The unit will remain in this state until a signal isapplied to terminals J or K (the reset terminals) at which time thesignal on terminal E is removed and the flip-flop is reset to zero and asignal appears on terminal L. The unit will remain in this state until asignal is applied. If the set and reset signals are appliedsimultaneously, both E and L signals will be removed and no signal willappear on the output terminals.

Time delay FIG. 6k shows the symbol for a time delay element. Itsoperation is such that a predetermined period of time after a one signalis removed from the input terminal, a one signal will appear on theoutput terminal.

Relay coil FIG. 61 shows the symbol used for a coil of a relay. Therelay coil is energized by applying a one signal to the coil.

Detailed description Referring now to FIG. 4, after the previousidentification code has been read, an one signal is applied to terminalM of one shot 101 causing a one signal to be produced on terminal Ewhich is applied to terminal X of one shot 103. When the one signal goesto zero, one shot 103 produces a one signal on terminal P which isapplied to terminal M of one shot 105. When the one signal from terminalP goes to zero, one shot 105 applies a one signal on output terminal 107to the three sweep oscillators 11-13 in FIG. 1 to reset the sweeposcillator.

Resetting is carried out on the negative going side of the one signalfrom terminal E of one shot 105. One shot 105 produces a zero signalfrom its terminal L at the same time which is applied to terminal M ofAND/NOT circuit 109. At this time, a zero signal is also applied toterminal N of AND/NOT circuit 109. AND/ NOT circuit 109 then applies aone signal to terminal M of one shot 101 so that when the zerosignalfrom terminal L of one shot goes negative, a one signal is applied toterminal M of AND/NOT 109. The one signal from terminal L of AND/NOT 109then goes positive causing one shot 101 to apply a one signal fromterminal E to terminal X of one shot 103. One shot 103 then produces aone signal on the positive going side of the one signal applied toterminal X which is applied to terminal M of one shot 105 causing oneshot 105 to produce another one signal from terminal E to reset thesweep oscillators again. The timing of the signals from one shots 103,105, and 101 is such that a reset pulse is produced from output terminalE of one shot 105 and delivered on output terminal 107 to reset thesweep after the sweep oscillator 11 has swept the first four frequenciesfrom 480 kc. to 450 kc. Thus, the sweep is reset after it has swept fourhits of the signal. Each of the three sweep oscillators 11-13 are resetbut sweep oscillator 11 is the only one we are now concerned with.

The signals received from the short receiving antenna 17 and gatereceiver 19 in FIG. 1 are applied to terminal 111 in FIG. 4. The inputpulses received on input terminal 111 are applied to inverting delaycircuit 113. Delay circuit 113 is a 50 microsecond delay circuit toinsure that the signal received on input terminal 111 is at least 50microseconds long. The zero signals are the significant signalsindicating a binary one. The zero signals received on input terminal 111are inverted to one signals by inverting delay circuit 113 and invertedback to a Zero signal by inverter 115. The zero signals from inverter115 are applied to terminal X of AND/ NOT circuit 117. A zero signal isapplied to terminal Y of AND/NOT circuit 117 at this time. With zerosignals applied to both terminals of AND/NOT circuit 117, AND/NOTcircuit 117 applies a one signal to the SET terminal of flip-flop 119 toset flip-flop to one. Flip-flop 119, set to one, applies a zero signalfrom output terminal W to terminal R of AND/ NOT circuit 121 and a zerosignal to terminal X of AND/ NOT circuit 123. AND/NOT circuit 123 alsohas a zero signal applied to its Y input terminal at this time so itapplies a one signal to the N terminal of AND/NOT circuit 109. AND/NOTcircuit 109 with a one signal applied to its N terminal is inhibitedfrom producing a one sig nal and can not apply a one signal to one shot101. The next time that one shot 105 applies a zero signal to terminal Mof AND/NOT 109, AND/NOT 109 does not apply a one signal to one shot 101;one shot 101 therefore does not apply a one signal to the input of oneshot 103 and one shot 103 does not apply a one signal to terminal M ofone shot 105. One shot 105 thereupon does not produce a one signal fromits output terminal E, no sweep reset signal is delivered on outputterminal 107 and the sweep oscillators 11-13 in FIG. 1 are not reset butcontinue on sweeping through the entire range of frequencies.

The inputs of the three frequency ranges from receiver 18 in FIG. 1 arereceived on input terminals 125, 126 and 127. The received signals areillustrated in the timing diagram in FIG. 2b. The input for thefrequency range 630 kc. through 520 kc. is received on input terminal125, the input for the frequency range 770 kc. through 660 kc. isreceived on input terminal 126 and the input for the frequency rangefrom 480 kc. though 370 kc. is received on input terminal 127. Thesignificant signals are zero signals, which are inverted to one signalsand delayed by delay circuits 128-130, respectively. The delay circuitsserve to make sure that a signal is at least 20 microseconds long beforeit is taken into consideration and thus eliminates a noise. The onesignals from delay circuits 128-130 are inverted back to zero signals byinverters 131-133 and applied to AND/NOT circuits 135-137. The input toterminal is applied to terminal H of AND/NOT circuit 135, the input toterminal 126 is applied to terminal T of AND/NOT circuit 136 and the 9input to terminal 127 is applied to terminal H of AND/ NOT circuit 137.

When the output from terminal E of one shot 105 goes to zero, it appliesa zero signal to terminal I of AND/NOT 135, a zero signal to terminal Uof AND/ NOT circuit 136 and a zero signal to terminal I of AND/ NOTcircuit 137.

When flip-flop 119 was set to one, it applied a zero signal to terminalR of AND/NOT circuit 121. Terminal T of AND/NOT 121 had a zero signalapplied thereto fITim output terminal L of one shot 105 at the lastreset pu se.

The zero signal received from gate receiver 19 in FIG. 1 on inputterminal 111, after delay and inversion to a one signal by delay circuit113, is applied to one shot 175 causing one shot 175 to produce a onesignal from its output terminal P which is delayed and inverted to azero signal by delay circuit 177 and applied as a zero signal toterminal X of AND/NOT circuit 179. AND/NOT circuit 179 has a one signalapplied to the Y terminal at this time so that AND/ NOT circuit 179applies a zero signal to terminal F of inverting OR circuit 181 and azero signal to terminal V of AND/NOT circuit 121. A zero signal isapplied to terminal F of inverting OR circuit 181 and as terminal K ofinverting OR circuit 181 also has a zero signal applied thereto at thistime. Inverting OR 181 applies a one signal continually to AND/NOTcircuit 179. This keeps AND/NOT circuit 179 producing a zero signal.

For the purposes of this immediate description, assume that terminal Uof AND/NOT circuit 121 has zero signals applied thereto at this timecausing AND/NOT circuit 121 to apply a one signal to the set inputterminal of flip-flop 139 to set that flip-flop to one. Flip-flop 139when set to one applies a zero signal to terminal F of AND/NOT circuit135, a zero signal to terminal R of AND/NOT circuit 136 and a zerosignal to terminal F of AND/NOT circuit 137.

Flip-flop 139 set to one also applies a zero signal from its zero outputterminal W to terminal Y of AND/ NOT 141, terminal N of AND/ NOT circuit143 and terminal H of AND/NOT circuit 145. This lets through the clockpulses in a manner to be explained.

The zero signals received on terminals 125-127 are applied after a delayand inversion to AND/ NOT circuits 135-137 as zero signals. As describedhereinbefore, the other terminals of these AND/NOT circuits 135-137 havezero signals applied to the other terminals thereof. AND/NOT circuits135-137 produce one signal-s which are delivered on output'terminals146-148 in response to the receipt of zero signals on the inputterminals 125-127. The one output signals on output terminals 146-147are applied to the set input terminals of the first shift register bitsin shift registers 52-54 in FIG. 1 to set the first shift register bitin each shift register to one. The set signals are illustrated in FIG.2a. A shift register is described in more detail with respect to FIG. 5.

Clock pulses are received on input terminals 154-156 in FIG. 4 from thethree clocks 41-43 in FIG. 1. These clock pulses are one signalsreceived as indicated in the timing diagram in FIG. 2d at the same timeas received signals will be received on input terminals 125-127. Theseclock pulses are applied to one shots 157-159 to cause one shots 157-159to produce zero signals from their output terminals. The zero signalsare applied to AND/ NOT circuits 141, 143 and 145. The output fromterminal L of one shot 159 is applied to terminal X of AND/NOT 141, theoutput from terminal L of one shot 158 is applied to terminal M ofAND/NOT 143, and the zero output signal from terminal W of one shot 157is applied to terminal F of one shot 145. It should be noted that theone shots 157-159 produce zero output signals on the zero going side ofthe clock pulses so that the zero outputs from one shots 157-159 aredelayed the width of the input clock pulses. Zero signals are applied 10to the other terminals of AND/NOT circuits 141, 143 and 145 as explainedhereinbefore so that when zero s1gnals are applied from the one shots toAND/NOT circuits 141, 143 and 145, AND/NOT circuits 141, 143 and 145produce one signals which are inverted to zero signals by invertingcircuits 161-163, inverted back to one signals by inverting amplifiers165-167 and applied as one signals to the shift inputs of shiftregisters 52-54 on output terminals 171-173 shown in FIG. 2 of thetiming diagram. I

The identification number is then read into the shift registers 52-54 ina manner which will be described specifically with respect to theinternal operation of a shift register shown in FIG. 5. The first bit ofthe shift registers is sequentially set and then shifted until alltwelve identification digits have been read into each of the shiftregisters.

At the end of the sweep of the frequencies by each of the three sweepgenerators, a one signal is received as a synchronization pulse on inputterminal 183. The zero signal received from gate receiver 19 in FIG. 1on terminal 111 stops as the signal repeating device has left the shortantenna so that a one signal is applied to terminal X of AND/NOT circuit117. AND/NOT circuit 117 then applies a zero signal to the SET terminalof flip-flop 119. The synchronism one signal received on input terminal183, after passing through OR circuit 185, is applied to the RESETterminal of flip-flop 119 to reset that flip-flop to zero and alsoapplied to the RESET terminal of flipflop 139 to reset that flip-flop tozero. The one signal from terminal 183 is also applied to terminal K ofinverting OR 181 causing inverting OR 181 to produce a zero signal whichis applied to terminal Y of AND/NOT circuit 179 causing AND/NOT circuit179 to produce a one signal which is applied to terminal F of invertingOR circuit 181. InventingOR 181 thus keeps producing a zero signal.AND/NOT circuit 179 also applies a one signal to terminal V of AND/NOTcircuit 121 and a one signal to terminal Y of AND/ NOT circuit 123.

AND/NOT circuit 121 with a one signal applied to terminal V applies azero signal to the SET input of flip-flop 139. AND/NOT 123 with a onesignal applied to its Y terminal applies a zero signal to terminal N ofAND/ NOT circuit 109 so that the sweep reset one shots the sweep of thefirst binary digits as hereinbefore de scribed.

Flip-flops 119 and 139 have been reset to zero so that flip-flop 119applies a one signal to terminal R of AND/ NOT circuit 121 and flip-flop139 applies a one signal to terminal H of AND/NOT circuit 145, terminalN of AND/NOT circuit 143, terminal Y of AND/NOT circuit 141, terminal Fof AND/NOT circuit 135, terminal R of AND/NOT circuit 136 and terminal Fof AND/NOT circuit 137. This inhibits the AND/NOT circuits 143, 141,145, 135, 136 and 137 from passing clock pulses and any received inputsignals.

The synchronization one signal received on terminal 183 on its zerogoing side causes one shot 185 to produce a one signal from outputterminal P to set flip-flop 187 to one. Flip-flop 187 set to one appliesa zero signal to terminal U of AND/NOT circuit 189 and a zero signal toterminal M of AND/NOT circuit 191. For the purposes of the immediatedescription, assume that a zero signal is applied to terminal V ofAND/NOT 189. AND/NOT 189 therefore produces a one signal which on itsnegative going side causes one shot 193 to produce a zero signal fromoutput terminal L which is inverted and amplified by inverting amplifier195 to a one signal and applied on output terminal 197 to all of thebuffer registers 58-60 in FIG. 1 to reset the buffer registers 58-60 tozero.

The one signal from output terminal E of one shot 193 in FIG. 4 isapplied to one shot 203 causing one shot 203 on the positive going sideof the one signal to produce a one signal which is inverted andamplified by inverting amplifier 205 and delivered on output terminal207 to 1 1 transfer elements 55-57 in FIG. 1 to transfer theidentification information therein from shift registers 52-54 to thebuffer registers. The one signal from one shot 203 on its positive goingside causes one shot 209 to produce a zero pulse on output terminal Lwhich is amplified and inverted to a one signal by inverting amplifier211 and delivered on output terminal 213 to shift registers 52-54 toreset all of the shift register bits therein to zero. The one signalfrom one shot 203 is also applied to terminal M of AND/ NOT circuit 217and also applied to the RESET terminal of flip-flop 187 to reset thatflipfiop to zero so that flip-flop 187 applies a one signal to terminalN of AND/NOT 191 and'a one signal to terminal U of AND/NOT 189.

As soon as the one signal from one shot 203 goes to zero, a zero signalis applied to terminal M of AND/ NOT 217, causing AND/NOT 217 to producea one signal which causes one shot'219 on the negative going side of thesignal to produce a one and a zero signal from its output terminals. Theone signal from output terminal P of one shot 219 is inverted anddelayed by delay circuit 221 to a longer zero signal, inverted back to aone signal by inverter 223 and applied as a one signal to terminal V ofAND/NOT 189. This prevents AND/NOT 189 from producing a further onesignal at this time to prevent one shot 193 from resetting or settingany of the buffer registers until after the number therein is punchedout in a manner to be described. The one signal from terminal P of one.shot 219 is also applied and amplified by amplifier 221 to energizerelay coil 223 to energize the clutch to punch out the first digit ofthe identification number. The number to be punched out is selected anddecoded in a manner to be referred to later.

The one signal from terminal P of one shot 219 is also applied toterminal M of AND/NOT circuit 225 causing the AND/NOT circuit 225 toapply a Zero signal to terminal F of decoder 227 and terminal F ofdecoder 229. A zero signal applied'to terminal F of decoder 227 andterminal F of decoder 229 opens these decoders so that they will decodethe number presented to them from readout counter 231.

Readout counter 231 consists of counter bits 232, 233, 234 and 235. Theone signal from one shot 219 is also applied to the PUL input terminal Iof counter hit 232 causing that counter bit to be complemented to oneregistering a count of one in the readout counter 231. The one and zerooutputs of readoutcounter 231 are applied to decoders 227' and 229 todecode the binary number resting in the readout counter 231 to a one outof nine output. The nine outputs from decoders 227 and 229 are onesignals which are inverted by inverters 241-249 to zero signals,amplified by amplifiers 251-259 anddelivered on output terminals 261-269to transfer element 61-69 to select one out of the nine digits ofinformation stored therein to be read out.

The clutch punch is activated as described hereinbefore to punch out thefirst digit of the identification number. The counter is then steppedforward one to select the next decimal number to be read out.

The zero signal from terminal W of one shot 219 produced at the sametime that the one signal is produced is applied to terminal F of oneshot 271 causing one shot 271 on the one going side of the zero signalto produce a zero signal from terminal L which isapplied to terminal Xof AND/NOT circuit 273. Terminal Y of AND/NOT circuit 273 has a zerosignal applied thereto at this time also from AND/ NOT circuit 275 forreasons which will be described. The zero output terminal L of counterbit 232 is applied to terminal F of AND/NOT 275, the one output terminalP of counter bit 233 is applied to terminal H of AND/NOT circuit 275,the one output terminal E of counter bit 234 is applied to terminal I ofAND/NOT circuit 275 and the zero output terminal W of counter bit 235 isapplied to terminal K of AND/NOT circuit 275. When all of these outputsare zero and applied to AND/NOT 275, the output of AND/NOT 275 will be aone signal. This is the occasion when readout counter 231 is counted tonine and has read out all of the numbers in the buffer registers 58-60in FIG. 1. As long as the readout counter 231 is counting between zeroand nine, a one signal is applied to at least one of the terminals ofAND/NOT circuit 275 causing AND/NOT circuit 275 to apply a zero signalto AND/ NOT 273.

AND/NOT 273 therefore produces a one signal upon the application of azero signal from terminal L of one shot 271, the one signal from AND/NOT273 being applied to terminal X of one shot 219. Upon the positive goingside of the one signal produced by AND/NOT 273, one shot 219 againproduces one and zero signals as hereinbefore described to cause thereadout counter 231 to count a further count of one and causing thepunch clutch to be activated to punch out another number as hereinbeforedescribed. The Zero signal from terminal W of one shot 219 is againapplied to one shot 271 as hereinbefore described to cause AND/ NOT 273to again activate one shot 219. This continues until readout counter 231has counted to nine whereupon, as hereinbefore described, zero signalsare applied to all of the terminals of AND/NOT 275 causing AND/NOT 275to apply a one signal to terminal Y of and AND/ NOT 273. AND/ NOT 273cannot therefore produce any further one signals and one shot 219 isde-activated. The one signal produced by AND/NOT 275 is also inverted byinverter 277 and applied as a zero signal to terminal H of AND/ NOT 279.As one shot 271 is no longer producing a one signal, one shot 271applies a zero signal to terminal F of AND/ NOT 279. One shot 219applies a zero signal to terminal I of AND/NOT 279 at the same time asone shot 271 applies a zero signal to terminal P so that zero signalsare applied to all of the terminals of one shot or AND/NOT 279 causingAND/NOT 279 to produce a one signal which is inverted by inverter 281 toa Zero signal and applied to terminal X of one shot 283.

The zero signal applied to terminal X of one shot 283 causes one shot283 to produce a one signal which is applied to the punch clutch tocause a carriage return.

Shift register A four bit portion of one of the shift registers andassociated buffer registers is shown in FIG. 5. This is a four bitportion thatshows the shift register hits, the transfer circuits, thebuffer registers and the transfer from the buffer register to thedecoder for readout. The shift register consists of four shift registerbits 301-304. Identification numbers are entered into this shiftregister serially by setting the first shift register bit 301 to one byapplying a one signal and pulse on input terminal 305 if a binary one isto be entered into the shift register 301 or applying a Zero signal toterminal 305. A binary zero is to be entered into shift register bit301. A zero signal is applied continually to the steer 1 terminal and a-6 volt or one signal is applied continually to the steer 0 inputterminal of shift register bit 301.

Because of the one signal continually applied to the steer 0 terminal,the last shift pulse applied to the PUL input terminal of shift registerbit 301 caused shift register bit 301 to be steered to zero. Shiftregister bit 301 is therefore zero at the time that a one or zero signalis applied to the SET input terminal 305. If a one signal is applied toterminal 305, shift register bit 301 is set to one. If a zero signal isapplied to terminal 305, shift register bit 301 remains reset to zero.

After shift register bit 301 has been set to one, or allowed to remainat zero, a shift signal is applied on terminal 307 to all of the P ULinput terminals of shift register bits 301-304. The shift pulse is asignificant time after the SET signal has been applied to terminal 305as shown in the timing diagram in FIGS. 2:! and 2c. Shift register bit301 set to one applies a one output signal from its one output terminalto the steer 1 terminal of shift register bit 302 or if it is reset tozero applies a one signal to the STD or steer terminal of shift registerbit 302. The shift pulse applied to the PUL input terminal of shiftregister bit 301 causes shift register bit 301 to be reset to Zerobecause of the one signal applied to the steer 0 terminal and causesshift register bit 302 to be either steered to one or steered to zerodepending on which terminal a one signal has been applied to. Thiscontinues on until a four bit number has been serially shifted intoshift register bits 301-304.

The identity number resting in shift register bits 301- 304 is shiftedto a buffer register consisting of four flipflops 311-314 by theapplication of a zero signal to the transfer terminal 309. The zeroterminals of shift register bits 301-3 04 are applied to terminals X ofAND/NOT circuit 321-324. Thus, if a shift register bit is set to one,its zero terminal applies a zero signal to terminal X of thecorresponding AND/ NOT circuit. When a zero signal is applied to thetransfer terminal 309 applying zero signals to terminals Y of AND/NOTcircuit 321-324, AND/NOT circuits 321-324 produce one signals from theiroutput terminal if the corresponding shift register bit 301-304 is setto one. The one signal from the output terminals of AND/NOT circuits321-324 set the corresponding flip-flops 311-31 4 to one. Flip-flops311-314 set to one apply a one signal to transfer network 325. Transfernetwork 325 does not transfer the signals applied thereto until a onesignal is applied to the read terminal 327. The read signal from inputterminal 327 is applied from one of the selected terminals 261-269 inFIG. 4.

Shift register bits 301-304 are reset to zero by the application of aone signal on RESET input terminal 331. Flip-flops 311-314 are reset bythe application of a one signal to RESET input terminal 333.

Multiplexer or transfer network 325 'when activated by the applicationof a one signal on input terminal 327 produces a one output signalcorresponding to the contents of flip-flop 311-314 on output terminals341-344. Output terminals 341-344 are applied to the decoding networkfor decoding before punch-out.

In summary, a new and improved identification interrogating system hasbeen described. This invention is particularly directed to theidentification system using piezolectric elements, each having adifferent preselected frequency response, whereby identification of theobject is made by the piezoelectric elements connected in the uniqueidentification device. This invention insures that the signals from anidentification device are not read until the identification device isentirely within the field of the receiving antenna. This is accomplishedby providing a second antenna shorter than and entirely within the fieldof the first antenna for receiving signals from the identificationdevice. When the second antenna receives signals indicating that theidentification device is entirely within the field of the first antenna,it gates the signals received by the first antenna.

While the invention has been explained and described with the aid ofparticular embodiments thereof, it will be understood that the inventionis not limited thereby and that many modifications retaining andutilizing the spirit thereof without departing essentially therefromwill occur to those skilled in the art in applying the invention tospecific operating environments and conditions. It is thereforecontemplated by the appended claims to cover all such modifications asfall within the scope and spirit of the invention.

What is claimed is:

1. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each piezoelectric element of a different preselected frequencyresponse, means for transmitting a variable frequency signal coveringthe frequency range of said signal repeating device, a first antenna forreceiving the signals reflected from said signal repeating devices, asecond antenna shorter than said first antenna and entirely Within thefield of said first antenna for receiving the signals reflected fromsaid signal repeating devices, and means responsive to the signalsreceived by said second antenna for gating the signals received by saidfirst antenna.

2. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each of a different preselected frequency response over a predeterminedfrequency range, means for transmitting a variable frequency signalcovering the frequency range of said signal repeating devices, a firstantenna for receiving the signls reflected from said signal repeatingdevices, a second antenna shorter than first antenna and entirely Withinthe field of said first antenna for receiving the signals reflected fromsaid signal repeating devices, means responsive to the sig nals receivedby said second antenna for gating the signals received by said firstantenna, and means for storing the signals gated from said firstantenna.

3. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each piezoelectric element of a different preselected frequency responseover a predetermined frequency range, means for transmitting a variablefrequency signal over said predetermined frequency range, meansresponsive to said transmitting means for providing timing signals insynchronism with the production of said variable signal, a first antennafor receiving the signals reflected from said signal repeating devices,a second antenna shorter than said first antenna and entirely within thefield of said first antenna for receiving the signals reflected fromsaid signal repeating devices, means responsive to the signals receivedby said second antenna for gating the signals received by said firstantenna, and means under the control of said timing means for storingthe frequency identified signals received by said first antenna.

4. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each of a different preselected frequency rsponse, means forinterrogating said signal repeating devices with a plurality of signalshaving different frequency ranges covering the frequency range of saidsignal repeating devices each of the different frequency ranges of saidplurality of signals being a division of the frequency range of saidsignal repeating devices, a first antenna for receiving the signalsreflected from said signal repeating devices, a second antenna shorterthan first antenna and entirely within the field of said first antennafor receiving the signals reflected from said signal repeating devices,and means responsive to the signals received by said second antenna forgating the signals received by said first antenna.

'5. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each of a different preselected frequency response over .a predeterminedfre quency range, means for transmitting variable frequency signals oversaid predetermined frequency range, a first antenna for receiving thesignals reflected from said signal repeating devices, a second antennashorter than said first antenna and entirely within the field of saidfirst antenna for receiving the signals reflected from said signalrepeating devices, means responsive to the signals received by saidsecond antenna for gating the signals received by said first antenna,means for storing the signals gated from said first antenna, bufferstorage means,

means responsive to the storage of said signals in said storage meansfor transferring said signals to said butler storage means, and meansresponsive to the transfer of said signals to said buffer storage meansfor controlling the readout of said signals.

6. In an identification interrogation system having a signal repeatingdevice associated with each object to be identified, each signalrepeating device having a plurality of selected piezoelectric elements,each of a different preselected frequency response over a predeterminedfrequency range, means for transmitting a variable frequency signal oversaid predetermined frequency range, means responsive to saidtransmitting means for providing timing signals in synchronism with theproduction of said variable signal, a first antenna for receiving thesignals reflected from said signal repeating devices, a second antennashorter than said first antenna and entirely within the field of saidfirst antenna for receiving the signals reflected from said signalrepeating devices, means under the control of said timing means forstoring the frequency identified signals received by said first antenna,buffer storagemeans, means responsive to the storage of said signals insaid storage means for transferring said signals to said buffer storagemeans, and means responsive to the transfer of said signals to saidbuffer storage means for controlling the readout of said signals.

References Cited by the Examiner UNITED STATES PATENTS 2,814,032 ll/57Agnew et al. 340-258 3,090,042 5/63 Kleist et al 3436.5 3,092,829 6/ 63Kleist 3436.5

CHESTER L. JUSTUS, Primary Examiner.

1. IN AN IDENTIFICATION INTERROGATION SYSTEM HAVING A SIGNAL REPEATINGDEVICE ASSOCIATED WITH EACH OBJECT TO BE IDENTIFIED, EACH SIGNALREPEATING DEVICE HAVING A PLURALITY OF SELECTED PIEZOELECTRIC ELEMENTS,EACH PIEZOELECTRIC ELEMENT OF A DIFFERENT PRESELECTED FREQUENCY RESPONSEMEANS FOR TRANSMITTING A VARIABLE FREQUENCY SIGNAL COVERING THEFREQUENCY RANGE OF SAID SIGNAL REPEATING DEVICE, A FIRST ANTENNA FORRECEIVING THE SIGNALS REFLECTED FROM SAID SIGNAL REPEATING DEVICES, ASECOND ANTENNA SHORTER THAN SAID FIRST ANTENNA AND ENTIRELY WITHIN THEFIELD OF SAID FIRST ANTENNA FOR RECEIVING THE SIGNALS REFLECTED FROMSAID SIGNAL REPEATING DEVICES, AND MEANS RESPONSIVE TO THE SIGNALSRECEIVED BY SAID SECOND ANTENNA FOR GATING THE SIGNALS RECEIVED BY SAIDFIRST ANTENNA.